#ifndef __RK3399_RESET_H__
#define __RK3399_RESET_H__

#ifdef __cplusplus
extern "C" {
#endif

#define RK3399_RESET_CORE_L0				(0)
#define RK3399_RESET_CORE_B0				(1)
#define RK3399_RESET_CORE_PO_L0				(2)
#define RK3399_RESET_CORE_PO_B0				(3)
#define RK3399_RESET_L2_L					(4)
#define RK3399_RESET_L2_B					(5)
#define RK3399_RESET_ADB_L					(6)
#define RK3399_RESET_ADB_B					(7)
#define RK3399_RESET_A_CCI					(8)
#define RK3399_RESET_A_CCIM0_NOC			(9)
#define RK3399_RESET_A_CCIM1_NOC			(10)
#define RK3399_RESET_DBG_NOC				(11)

#define RK3399_RESET_CORE_L0_T				(16)
#define RK3399_RESET_CORE_L1				(17)
#define RK3399_RESET_CORE_L2				(18)
#define RK3399_RESET_CORE_L3				(19)
#define RK3399_RESET_CORE_PO_L0_T			(20)
#define RK3399_RESET_CORE_PO_L1				(21)
#define RK3399_RESET_CORE_PO_L2				(22)
#define RK3399_RESET_CORE_PO_L3				(23)
#define RK3399_RESET_A_ADB400_GIC2COREL		(24)
#define RK3399_RESET_A_ADB400_COREL2GIC		(25)
#define RK3399_RESET_P_DBG_L				(26)
#define RK3399_RESET_L2_L_T					(28)
#define RK3399_RESET_ADB_L_T				(29)
#define RK3399_RESET_A_RKPERF_L				(30)
#define RK3399_RESET_PVTM_CORE_L			(31)

#define RK3399_RESET_CORE_B0_T				(32)
#define RK3399_RESET_CORE_B1				(33)
#define RK3399_RESET_CORE_PO_B0_T			(36)
#define RK3399_RESET_CORE_PO_B1				(37)
#define RK3399_RESET_A_ADB400_GIC2COREB		(40)
#define RK3399_RESET_A_ADB400_COREB2GIC		(41)
#define RK3399_RESET_P_DBG_B				(42)
#define RK3399_RESET_L2_B_T					(43)
#define RK3399_RESET_ADB_B_T				(45)
#define RK3399_RESET_A_RKPERF_B				(46)
#define RK3399_RESET_PVTM_CORE_B			(47)

#define RK3399_RESET_A_CCI_T				(50)
#define RK3399_RESET_A_CCIM0_NOC_T			(51)
#define RK3399_RESET_A_CCIM1_NOC_T			(52)
#define RK3399_RESET_A_ADB400M_PD_CORE_B_T	(53)
#define RK3399_RESET_A_ADB400M_PD_CORE_L_T	(54)
#define RK3399_RESET_DBG_NOC_T				(55)
#define RK3399_RESET_DBG_CXCS				(56)
#define RK3399_RESET_CCI_TRACE				(57)
#define RK3399_RESET_P_CCI_GRF				(58)

#define RK3399_RESET_A_CENTER_MAIN_NOC		(64)
#define RK3399_RESET_A_CENTER_PERI_NOC		(65)
#define RK3399_RESET_P_CENTER_MAIN			(66)
#define RK3399_RESET_P_DDRMON				(67)
#define RK3399_RESET_P_CIC					(68)
#define RK3399_RESET_P_CENTER_SGRF			(69)
#define RK3399_RESET_DDR0_MSCH				(70)
#define RK3399_RESET_DDRCFG0_MSCH			(71)
#define RK3399_RESET_DDR0					(72)
#define RK3399_RESET_DDRPHY0				(73)
#define RK3399_RESET_DDR1_MSCH				(74)
#define RK3399_RESET_DDRCFG1_MSCH			(75)
#define RK3399_RESET_DDR1					(76)
#define RK3399_RESET_DDRPHY1				(77)
#define RK3399_RESET_DDR_CIC				(78)
#define RK3399_RESET_PVTM_DDR				(79)

#define RK3399_RESET_A_VCODEC_NOC			(80)
#define RK3399_RESET_A_VCODEC				(81)
#define RK3399_RESET_H_VCODEC_NOC			(82)
#define RK3399_RESET_H_VCODEC				(83)
#define RK3399_RESET_A_VDU_NOC				(88)
#define RK3399_RESET_A_VDU					(89)
#define RK3399_RESET_H_VDU_NOC				(90)
#define RK3399_RESET_H_VDU					(91)
#define RK3399_RESET_VDU_CORE				(92)
#define RK3399_RESET_VDU_CA					(93)

#define RK3399_RESET_A_IEP_NOC				(96)
#define RK3399_RESET_A_VOP_IEP				(97)
#define RK3399_RESET_A_IEP					(98)
#define RK3399_RESET_H_IEP_NOC				(99)
#define RK3399_RESET_H_IEP					(100)
#define RK3399_RESET_A_RGA_NOC				(102)
#define RK3399_RESET_A_RGA					(103)
#define RK3399_RESET_H_RGA_NOC				(104)
#define RK3399_RESET_H_RGA					(105)
#define RK3399_RESET_RGA_CORE				(106)
#define RK3399_RESET_EMMC_NOC				(108)
#define RK3399_RESET_EMMC					(109)
#define RK3399_RESET_EMMC_GRF				(110)

#define RK3399_RESET_A_PERIHP_NOC			(112)
#define RK3399_RESET_P_PERIHP_GRF			(113)
#define RK3399_RESET_H_PERIHP_NOC			(114)
#define RK3399_RESET_USBHOST0				(115)
#define RK3399_RESET_HOSTC0_AUX				(116)
#define RK3399_RESET_HOST0_ARB				(117)
#define RK3399_RESET_USBHOST1				(118)
#define RK3399_RESET_HOSTC1_AUX				(119)
#define RK3399_RESET_HOST1_ARB				(120)
#define RK3399_RESET_SDIO0					(121)
#define RK3399_RESET_SDMMC					(122)
#define RK3399_RESET_HSIC					(123)
#define RK3399_RESET_HSIC_AUX				(124)
#define RK3399_RESET_AHB1TOM				(125)
#define RK3399_RESET_P_PERIHP_NOC			(126)
#define RK3399_RESET_HSICPHY				(127)

#define RK3399_RESET_A_PCIE					(128)
#define RK3399_RESET_P_PCIE					(129)
#define RK3399_RESET_PCIE_CORE				(130)
#define RK3399_RESET_PCIE_MGMT				(131)
#define RK3399_RESET_PCIE_MGMT_STICKY		(132)
#define RK3399_RESET_PCIE_PIPE				(133)
#define RK3399_RESET_PCIE_PM				(134)
#define RK3399_RESET_PCIEPHY				(135)
#define RK3399_RESET_A_GMAC_NOC				(136)
#define RK3399_RESET_A_GMAC					(137)
#define RK3399_RESET_P_GMAC_NOC				(138)
#define RK3399_RESET_P_GMAC_GRF				(140)
#define RK3399_RESET_HSICPHY_POR			(142)
#define RK3399_RESET_HSICPHY_UTMI			(143)

#define RK3399_RESET_USB2PHY0_POR			(144)
#define RK3399_RESET_USB2PHY0_UTMI_PORT0	(145)
#define RK3399_RESET_USB2PHY0_UTMI_PORT1	(146)
#define RK3399_RESET_USB2PHY0_EHCIPHY		(147)
#define RK3399_RESET_UPHY0_PIPE_L00			(148)
#define RK3399_RESET_UPHY0					(149)
#define RK3399_RESET_UPHY0_TCPDPWRUP		(150)
#define RK3399_RESET_USB2PHY1_POR			(152)
#define RK3399_RESET_USB2PHY1_UTMI_PORT0	(153)
#define RK3399_RESET_USB2PHY1_UTMI_PORT1	(154)
#define RK3399_RESET_USB2PHY1_EHCIPHY		(155)
#define RK3399_RESET_UPHY1_PIPE_L00			(156)
#define RK3399_RESET_UPHY1					(157)
#define RK3399_RESET_UPHY1_TCPDPWRUP		(158)

#define RK3399_RESET_A_PERILP0_NOC			(160)
#define RK3399_RESET_A_DCF					(161)
#define RK3399_RESET_GIC500					(162)
#define RK3399_RESET_DMAC0_PERILP0			(163)
#define RK3399_RESET_DMAC1_PERILP0			(164)
#define RK3399_RESET_TZMA					(165)
#define RK3399_RESET_INTMEM					(166)
#define RK3399_RESET_ADB400_MST0			(167)
#define RK3399_RESET_ADB400_MST1			(168)
#define RK3399_RESET_ADB400_SLV0			(169)
#define RK3399_RESET_ADB400_SLV1			(170)
#define RK3399_RESET_H_PERILP0				(171)
#define RK3399_RESET_H_PERILP0_NOC			(172)
#define RK3399_RESET_ROM					(173)
#define RK3399_RESET_CRYPTO_S				(174)
#define RK3399_RESET_CRYPTO_M				(175)

#define RK3399_RESET_P_DCF					(176)
#define RK3399_RESET_CM0S_NOC				(177)
#define RK3399_RESET_CM0S					(178)
#define RK3399_RESET_CM0S_DBG				(179)
#define RK3399_RESET_CM0S_PO				(180)
#define RK3399_RESET_CRYPTO					(181)
#define RK3399_RESET_P_PERILP1_SGRF			(182)
#define RK3399_RESET_P_PERILP1_GRF			(183)
#define RK3399_RESET_CRYPTO1_S				(184)
#define RK3399_RESET_CRYPTO1_M				(185)
#define RK3399_RESET_CRYPTO1				(186)
#define RK3399_RESET_GIC_NOC				(188)
#define RK3399_RESET_SD_NOC					(189)
#define RK3399_RESET_SDIOAUDIO_BRG			(190)

#define RK3399_RESET_H_PERILP1				(192)
#define RK3399_RESET_H_PERILP1_NOC			(193)
#define RK3399_RESET_H_I2S0_8CH				(194)
#define RK3399_RESET_H_I2S1_8CH				(195)
#define RK3399_RESET_H_I2S2_8CH				(196)
#define RK3399_RESET_H_SPDIF_8CH			(197)
#define RK3399_RESET_P_PERILP1_NOC			(198)
#define RK3399_RESET_P_EFUSE_1024			(199)
#define RK3399_RESET_P_EFUSE_1024S			(200)
#define RK3399_RESET_P_I2C0					(201)
#define RK3399_RESET_P_I2C1					(202)
#define RK3399_RESET_P_I2C2					(203)
#define RK3399_RESET_P_I2C3					(204)
#define RK3399_RESET_P_I2C4					(205)
#define RK3399_RESET_P_I2C5					(206)
#define RK3399_RESET_P_MAILBOX0				(207)

#define RK3399_RESET_P_UART0				(208)
#define RK3399_RESET_P_UART1				(209)
#define RK3399_RESET_P_UART2				(210)
#define RK3399_RESET_P_UART3				(211)
#define RK3399_RESET_P_SARADC				(212)
#define RK3399_RESET_P_TSADC				(213)
#define RK3399_RESET_P_SPI0					(214)
#define RK3399_RESET_P_SPI1					(215)
#define RK3399_RESET_P_SPI2					(216)
#define RK3399_RESET_P_SPI4					(217)
#define RK3399_RESET_P_SPI5					(218)
#define RK3399_RESET_SPI0					(219)
#define RK3399_RESET_SPI1					(220)
#define RK3399_RESET_SPI2					(221)
#define RK3399_RESET_SPI4					(222)
#define RK3399_RESET_SPI5					(223)

#define RK3399_RESET_I2S0_8CH				(224)
#define RK3399_RESET_I2S1_8CH				(225)
#define RK3399_RESET_I2S2_8CH				(226)
#define RK3399_RESET_SPDIF_8CH				(227)
#define RK3399_RESET_UART0					(228)
#define RK3399_RESET_UART1					(229)
#define RK3399_RESET_UART2					(230)
#define RK3399_RESET_UART3					(231)
#define RK3399_RESET_TSADC					(232)
#define RK3399_RESET_I2C0					(233)
#define RK3399_RESET_I2C1					(234)
#define RK3399_RESET_I2C2					(235)
#define RK3399_RESET_I2C3					(236)
#define RK3399_RESET_I2C4					(237)
#define RK3399_RESET_I2C5					(238)
#define RK3399_RESET_SDIOAUDIO_NOC			(239)

#define RK3399_RESET_A_VIO_NOC				(240)
#define RK3399_RESET_A_HDCP_NOC				(241)
#define RK3399_RESET_A_HDCP					(242)
#define RK3399_RESET_H_HDCP_NOC				(243)
#define RK3399_RESET_H_HDCP					(244)
#define RK3399_RESET_P_HDCP_NOC				(245)
#define RK3399_RESET_P_HDCP					(246)
#define RK3399_RESET_P_HDMI_CTRL			(247)
#define RK3399_RESET_P_DP_CTRL				(248)
#define RK3399_RESET_S_DP_CTRL				(249)
#define RK3399_RESET_C_DP_CTRL				(250)
#define RK3399_RESET_P_MIPI_DSI0			(251)
#define RK3399_RESET_P_MIPI_DSI1			(252)
#define RK3399_RESET_DP_CORE				(253)
#define RK3399_RESET_DP_I2S					(254)

#define RK3399_RESET_GASKET					(256)
#define RK3399_RESET_VIO_GRF				(258)
#define RK3399_RESET_DPTX_SPDIF_REC			(259)
#define RK3399_RESET_HDMI_CTRL				(260)
#define RK3399_RESET_HDCP_CTRL				(261)
#define RK3399_RESET_A_ISP0_NOC				(262)
#define RK3399_RESET_A_ISP1_NOC				(263)
#define RK3399_RESET_H_ISP0_NOC				(266)
#define RK3399_RESET_H_ISP1_NOC				(267)
#define RK3399_RESET_H_ISP0					(268)
#define RK3399_RESET_H_ISP1					(269)
#define RK3399_RESET_ISP0					(270)
#define RK3399_RESET_ISP1					(271)

#define RK3399_RESET_A_VOP0_NOC				(272)
#define RK3399_RESET_A_VOP1_NOC				(273)
#define RK3399_RESET_A_VOP0					(274)
#define RK3399_RESET_A_VOP1					(275)
#define RK3399_RESET_H_VOP0_NOC				(276)
#define RK3399_RESET_H_VOP1_NOC				(277)
#define RK3399_RESET_H_VOP0					(278)
#define RK3399_RESET_H_VOP1					(279)
#define RK3399_RESET_D_VOP0					(280)
#define RK3399_RESET_D_VOP1					(281)
#define RK3399_RESET_VOP0_PWM				(282)
#define RK3399_RESET_VOP1_PWM				(283)
#define RK3399_RESET_P_EDP_NOC				(284)
#define RK3399_RESET_P_EDP_CTRL				(285)

#define RK3399_RESET_A_GPU					(288)
#define RK3399_RESET_A_GPU_NOC				(289)
#define RK3399_RESET_A_GPU_GRF				(290)
#define RK3399_RESET_PVTM_GPU				(291)
#define RK3399_RESET_A_USB3_NOC				(292)
#define RK3399_RESET_A_USB3_OTG0			(293)
#define RK3399_RESET_A_USB3_OTG1			(294)
#define RK3399_RESET_A_USB3_GRF				(295)
#define RK3399_RESET_PMU					(296)

#define RK3399_RESET_P_TIMER0_5				(304)
#define RK3399_RESET_TIMER0					(305)
#define RK3399_RESET_TIMER1					(306)
#define RK3399_RESET_TIMER2					(307)
#define RK3399_RESET_TIMER3					(308)
#define RK3399_RESET_TIMER4					(309)
#define RK3399_RESET_TIMER5					(310)
#define RK3399_RESET_P_TIMER6_11			(311)
#define RK3399_RESET_TIMER6					(312)
#define RK3399_RESET_TIMER7					(313)
#define RK3399_RESET_TIMER8					(314)
#define RK3399_RESET_TIMER9					(315)
#define RK3399_RESET_TIMER10				(316)
#define RK3399_RESET_TIMER11				(317)
#define RK3399_RESET_P_INTR_ARB_PMU			(318)
#define RK3399_RESET_P_ALIVE_SGRF			(319)

#define RK3399_RESET_P_GPIO2				(320)
#define RK3399_RESET_P_GPIO3				(321)
#define RK3399_RESET_P_GPIO4				(322)
#define RK3399_RESET_P_GRF					(323)
#define RK3399_RESET_P_ALIVE_NOC			(324)
#define RK3399_RESET_P_WDT0					(325)
#define RK3399_RESET_P_WDT1					(326)
#define RK3399_RESET_P_INTR_ARB				(327)
#define RK3399_RESET_P_UPHY0_DPTX			(328)
#define RK3399_RESET_P_UPHY0_APB			(330)
#define RK3399_RESET_P_UPHY0_TCPHY			(332)
#define RK3399_RESET_P_UPHY1_TCPHY			(333)
#define RK3399_RESET_P_UPHY0_TCPDCTRL		(334)
#define RK3399_RESET_P_UPHY1_TCPDCTRL		(335)

#define RK3399_RESET_P_NOC					(336)
#define RK3399_RESET_P_INTMEM				(337)
#define RK3399_RESET_H_CM0S					(338)
#define RK3399_RESET_H_CM0S_NOC				(339)
#define RK3399_RESET_DBG_CM0S				(340)
#define RK3399_RESET_PO_CM0S				(341)
#define RK3399_RESET_P_SPI3					(342)
#define RK3399_RESET_SPI3					(343)
#define RK3399_RESET_P_TIMER_0_1			(344)
#define RK3399_RESET_P_TIMER_0				(345)
#define RK3399_RESET_P_TIMER_1				(346)
#define RK3399_RESET_P_UART4				(347)
#define RK3399_RESET_UART4					(348)
#define RK3399_RESET_P_WDT					(349)

#define RK3399_RESET_P_I2C6					(352)
#define RK3399_RESET_P_I2C7					(353)
#define RK3399_RESET_P_I2C8					(354)
#define RK3399_RESET_P_MAILBOX				(355)
#define RK3399_RESET_P_RKPWM				(356)
#define RK3399_RESET_P_PMUGRF				(357)
#define RK3399_RESET_P_SGRF					(358)
#define RK3399_RESET_P_GPIO0				(359)
#define RK3399_RESET_P_GPIO1				(360)
#define RK3399_RESET_P_CRU					(361)
#define RK3399_RESET_P_INTR					(362)
#define RK3399_RESET_PVTM					(363)
#define RK3399_RESET_I2C6					(364)
#define RK3399_RESET_I2C7					(365)
#define RK3399_RESET_I2C8					(366)

#ifdef __cplusplus
}
#endif

#endif /* __RK3399_RESET_H__ */
